HOW PHYSICALLY AWARE INTERCONNECT IP BOLSTERS SOC DESIGN”

HOW PHYSICALLY AWARE INTERCONNECT IP BOLSTERS SOC DESIGN

 By developing physical awareness, network-on-chip (NoC) technology, which joins IP blocks in extremely complicated system-on-chip (SoC) designs, has advanced to the next logical level. That expedites the discovery of the necessary area to establish an ideal NoC topology at the front-end and expedites temporal closure at the back-end, claims Andy Nightingale, vice president of product marketing at Arteris.

FlexNoC 5, the company's next-generation connectivity IP and first physically aware NoC technology, has been unveiled by Arteris. With fewer layout team iterations and faster physical convergence than human improvements, it aims to enable SoC architecture teams, logic designers, and integrators.

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Table 1 6,000+ pipeline registers may be needed for a large 7-nm SoC, and completing the insertion level by becoming conscious of one's body. That expedites the discovery of the necessary area to establish an ideal NoC topology at the front-end and expedites temporal closure at the back-end, claims Andy Nightingale, vice president of product marketing at Arteris.

In order to achieve the power, performance, and area (PPA) goals for SoC designs, Arteris has disclosed extensive construction of limitations for the physical location of units, as well as protracted NoC placement plus route iterations. In this case, a physically aware interconnect IP eliminates iterations while reducing the time required for various manual operations.

The CEO of Sondrel, Graham Curren, recognises that physical limitations have always been a problem and are significantly more of a problem below 16-nm geometries. FlexNoC 5 has been used by Sondrel, a provider of IC design services, in its Curren claims that this has made it possible for RTL teams to confirm that architectures adhere to physical restrictions and give better starting points for location and route. bespoke SoC design project.

Without physical awareness, IC makers can produce SoC architectures that are challenging or even impossible to put and route, said Charles Janac, president and CEO of Arteris. In particular for geometries of 16 nm and smaller, "that may result in repeated turns, overall project delay concerns, and increased project expenses."

According to Figure 2, the FlexNoC 5 interconnect IP performs physical convergence 5X faster and with less iterations than manual improvements. Origin: Arteris

According to Arteris, FlexNoC 5 enables physical convergence of the back-end physical design time and effort to occur up to 5X faster. that gets ready the NoC IP that has been physically tuned for use in place-and-route implementations and physical synthesis. Moreover, FlexNoC 5 adds support for IEEE 1685 IP-XACT and Arm AMBA 5 protocols, as well as a communication flow with Arteris Magillem allowing NoC integration with other SoC IP blocks.

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